TSMC's fourth generation of 16nm FinFET process development, collectively referred to as 12nm process technology, began with the development of 12-nanometer NeoFuse IP, following the 16-nanometer FinFET Finisher process, the TSMC and Li-wang in the advanced process on the re-cooperation .
TSMC's 16-nanometer (nm) process is entering the 16nm fourth-generation process technology with 16 nanometer FinFETs, 16FF + and 16FFCs, with Apple, MediaTek, Hassle, Xilinx and NVIDIA orders coming in. TSMC is also rare Change strategy to launch the revision process, which is 12-nanometer process technology to attract more customers to vote in order to enhance 12-inch fab capacity utilization. bcm4319gkubg
With TSMC entering the 12-nanometer manufacturing process generation, non-volatile embedded eNVM IP supplier Li Wang also with TSMC's 12-nanometer process development NeoFuse IP. The 12 nanometer FinFET process is the fourth generation of the 16 nanometer FinFET family, with 12 nanometers of lower leakage characteristics and cost advantages compared to previous generations, Liwang and TSMC have been working together from the first generation of 16 nanometer FinFETs, To the latest fourth-generation process, in each generation process platform are NeoFuse IP.
In addition, Liwon also completed the reliability verification process on the 16nm FinFET (16FFC) process, and customers have embedded the NeoFuse IP in the product and completed the design decision (Tape Out).
The 16FFC process, compared to the 16-nanofetower FinFET (16FF +) process, has the advantage of being more cost-effective and less power-hungry in the mainstream market, and is favored by many end applications, including smartphones, consumer electronics, Wear devices, etc., while NeoFuse IP in addition to widely used by customers in the 16-nanometer FinFET Finisher process, the write heat resistance is increased to 125 degrees, but also makes the operation more flexible, and can be more flexible Support more high-end applications. 88e1112c2-nnc1
On the whole, NeoFuse IP is the first to complete the reliability verification of TSMC's 16-nanometer FinFET process, showing the development capability of high-end process technology and the solid technical partnership with TSMC.