7 nanometer technology candidates: IMEC promising GAA NWFET technology

(IMEC) in the 2016 International Electronic Components Conference (IEEE International Electron Devices Meeting (IEDM) for the first time proposed by the vertical stacking of silicon nanowires around the gate (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) , The key technology of which is the dual-power metal gate, makes the critical voltages of the n-type and p-type devices equal, and for technology candidates below 7 nanometers, IMEC looks to surround gated nanowire transistors (GAA NWFETs) ) Will be selected.

Belgium Microelectronics Research Center and many of the world's semiconductor manufacturers, system manufacturers are advanced process and innovative technology partners; Among them, the CMOS advanced micro-scaling technology research key partners include TSMC, Samsung Electronics (SamsungElectronics), Qualcomm Qualcomm, GlobalFoundries, Micron, Intel, SK Hynix, Sony and Huawei. ms27110

For the semiconductor 7 nanometer process, who can take over the FinFET technology? Currently, it appears that the gated-nanowire transistor (GAA NWFET) is the most likely candidate to successfully break through the 7-nanometer FinFET process, according to the Belgian Microelectronics Research Center.

Belgium Microelectronics further analysis, because the GAA NWFET has a high static control capability, can achieve CMOS miniature, in the horizontal configuration, is also a natural extension of the mainstream FinFET technology, you can vertically stack multiple horizontal nanowires to maximize each coverage area Of the drive current.

Furthermore, the Belgian Microelectronics Research Center has also studied the impact of new structures on the performance of electrostatic discharge (ESD), and published electrostatic discharge protection diodes, so that the development of GAA nano-MOSFETs breakthrough, indirectly help fin field effect transistor (FinFET) continue to more advanced process technology development. mis-20054

2016 Belgium Microelectronics Research Center shows a vertical stack, made by the diameter of 8 nanometer silicon nanowire GAA FET, the static control of these transistors from n-FETs and p-FETs made, with n-type and p Type components of the same critical voltage, because the key in integrated circuit technology is the use of dual-function metal gate, making the n-FET and p-FET threshold voltage can be set independently.

And in this step, the P-type work function metal (PWFM) is used in the trench gate of all the elements and then the selective etching of the P-type work function metal to the nanocrystalline hafnium oxide (HfO2) to the n-FET , Followed by an N-type work function metal.

In addition, for the impact of critical electrostatic discharge (ESD), Belgium Microelectronics proposed two different electrostatic discharge protection diodes, respectively, for the gate diodes and shallow trench isolation (STI) diodes. Among them, STI diode because the secondary breakdown current (It2) and the ratio of parasitic capacitance on the better performance, so that is a good ESD protection devices.

Furthermore, measurements and TCAD simulations have demonstrated that GAA nanowire diodes maintain electrostatic discharge performance compared to Bulk FinFETs (Bulk FinFET) diodes.

Dan Mocuta, director of logic and integrated circuits at the Belgian Microelectronics Research Center, said that the integrated circuit technology in the GAA silicon CMOS technology, ESD protection results, is an important achievement in achieving 7 nanometer or below process.